With aggressive process scaling, raw bit error rate (RBER) of NAND flash is becoming poorer and poorer. To maintain the same level of reliability, solid state drive/disk (SSD) controllers are adopting soft decoded error correction codes, such as low density parity check (LDPC) codes. Soft decoded error correction codes are more powerful in correcting errors, but the input to the decoder needs to be soft information. The soft information is typically in the form of a log likelihood ratio (LLR). LDPC codes have been successfully used on hard disk drives (HDDs), where the LLRs of LDPC decoders are provided by a channel detector (typically a soft Viterbi decoder). A very sophisticated signal processing system handles channel variation and ensures that the LLRs input to the LDPC decoders are close to optimal. NAND flash channels are highly time variant due to a number of factors, such as retention, program and erase (P/E) cycling effect, read disturb, etc. A signal processing system similar to the one used in HDDs and applicable to NAND flash channels is not available. As a result, optimal reads cannot be guaranteed for all pages. Some pages can be read with high reliability, while others are not. A mechanism that is able to conveniently deliver different LLRs to LDPC decoders and conveniently control decoding parameters (such as number of iterations, scaling factor, bias of min-sum algorithm, etc.) is needed, in order to achieve the best uncorrectable BER (UBER) and the best throughput performance.
It would be desirable to have a method and/or apparatus for implementing dynamic per-decoder control of log likelihood ratio (LLR) and decoding parameters.